From: Marco Peereboom (slashpeereboom.us)
Date: Wed Sep 03 2008 - 09:21:24 CDT

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Why static?

On Tue, Sep 02, 2008 at 10:51:41PM -0700, Matthew Clarke wrote:
> Hi.
>
> I wanted to give the DRI stuff that oga has been working so hard on
> a try. The X server found radeondrm(4) fine after I enabled it via
> config(8) but then complained that agp(4) wasn't working. X was right;
> this machine has the NVIDIA nForce2 core chipset, and there's no support
> for agp(4) on that. A search through the archives of this list turned up
> a posting from March of 2006 in which Dimitry Andric provided a patch to
> add that support.
>
> The following is that patch, but tweaked so that it applies to current.
> My thanks to Mr. Andric and the original developers for the heavy lifting;
> all I had to do was tweak things to get the patch to apply and compile.
>
> With this patch, and radeondrm(4) enabled, I now get:
>
> agp0 at vga1: aperture at 0xe0000000, size 0x4000000
> radeondrm0 at vga1 ATI Radeon AP 9600(0), 1.29.0 20080613
>
> That's an ATI Radeon 9600 PRO AGP card in the AGP slot on this mainboard,
> which is an MSI K7N2 Delta-L (MS-6570).
>
> I've put a full dmesg after the patch. Tested on i386 only; I see that
> agp(4) is also in the amd64 kernel, but I have no amd64 system.
>
> X reports that DRI is there and glxgears(1) and the GL modes in xlock(1)
> all run much faster. Marathon and marathoninfinity (from packages)
> both start up OK and look nice, but I haven't really had time to play.
> Celestia (also from packages) throws a software fallback warning from the
> Mesa r300 driver and then crashes with a propolice-caught stack overflow.
> I haven't tried any other GL programs yet.
>
> patch:
> ------------------------------------------------------------------------------
> Index: sys/arch/i386/conf/files.i386
> ===================================================================
> RCS file: /cvs/src/sys/arch/i386/conf/files.i386,v
> retrieving revision 1.182
> diff -u -r1.182 files.i386
> --- sys/arch/i386/conf/files.i386 8 Jul 2008 05:22:00 -0000 1.182
> +++ sys/arch/i386/conf/files.i386 1 Sep 2008 02:41:24 -0000
> -101,7 +101,7
> file arch/i386/pci/pcic_pci_machdep.c pcic_pci
>
> # AGP devices
> -device agp: agp_ali, agp_amd, agp_i810, agp_intel, agp_sis, agp_via
> +device agp: agp_ali, agp_amd, agp_i810, agp_intel, agp_nvidia, agp_sis, agp_via
> attach agp at agpbus
> file arch/i386/pci/agp_machdep.c agp
>
> Index: sys/dev/pci/agp.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/agp.c,v
> retrieving revision 1.25
> diff -u -r1.25 agp.c
> --- sys/dev/pci/agp.c 17 Aug 2008 21:31:38 -0000 1.25
> +++ sys/dev/pci/agp.c 1 Sep 2008 05:44:14 -0000
> -52,6 +52,7
> #include "agp_apple.h"
> #include "agp_i810.h"
> #include "agp_intel.h"
> +#include "agp_nvidia.h"
> #include "agp_sis.h"
> #include "agp_via.h"
>
> -97,6 +98,10
> #if NAGP_INTEL > 0
> { PCI_VENDOR_INTEL, -1, agp_intel_attach },
> #endif
> +#if NAGP_NVIDIA > 0
> + { PCI_VENDOR_NVIDIA,PCI_PRODUCT_NVIDIA_NFORCE_PCHB,agp_nvidia_attach },
> + { PCI_VENDOR_NVIDIA,PCI_PRODUCT_NVIDIA_NFORCE2_PCHB,agp_nvidia_attach },
> +#endif
> #if NAGP_SIS > 0
> { PCI_VENDOR_SIS, -1, agp_sis_attach },
> #endif
> Index: sys/dev/pci/agp_nvidia.c
> ===================================================================
> RCS file: sys/dev/pci/agp_nvidia.c
> diff -N sys/dev/pci/agp_nvidia.c
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ sys/dev/pci/agp_nvidia.c 1 Sep 2008 05:31:41 -0000
> -0,0 +1,392
> +/* $OpenBSD$ */
> +
> +/*-
> + * Copyright (c) 2003 Matthew N. Dodd <winter_(_at_)_jurai_(_dot_)_net>
> + * All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + *
> + * $FreeBSD: src/sys/pci/agp_nvidia.c,v 1.11 2005/12/20 21:12:26 jhb Exp $
> + */
> +
> +/*
> + * Written using information gleaned from the
> + * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
> + */
> +
> +#include <sys/param.h>
> +#include <sys/kernel.h>
> +#include <sys/malloc.h>
> +#include <sys/systm.h>
> +#include <sys/proc.h>
> +#include <sys/conf.h>
> +#include <sys/device.h>
> +#include <sys/lock.h>
> +#include <sys/agpio.h>
> +
> +#include <dev/pci/pcivar.h>
> +#include <dev/pci/pcireg.h>
> +#include <dev/pci/vga_pcivar.h>
> +#include <dev/pci/agpvar.h>
> +#include <dev/pci/agpreg.h>
> +#include <dev/pci/pcidevs.h>
> +
> +#include <machine/bus.h>
> +#include <machine/cpufunc.h>
> +
> +struct agp_nvidia_softc {
> + u_int32_t initial_aperture; /* aperture size at startup */
> + struct agp_gatt * gatt;
> +
> + pcitag_t tag; /* AGP Controller */
> + pcitag_t mc1_tag; /* Memory Controller */
> + pcitag_t mc2_tag; /* Memory Controller */
> + pcitag_t btag; /* Bridge */
> +
> + u_int32_t wbc_mask;
> + int num_dirs;
> + int num_active_entries;
> + off_t pg_offset;
> +};
> +
> +static u_int32_t agp_nvidia_get_aperture(struct agp_softc *);
> +static int agp_nvidia_set_aperture(struct agp_softc *, u_int32_t);
> +static int agp_nvidia_bind_page(struct agp_softc *, off_t, bus_addr_t);
> +static int agp_nvidia_unbind_page(struct agp_softc *, off_t);
> +static void agp_nvidia_flush_tlb(struct agp_softc *);
> +static int nvidia_init_iorr(u_int32_t, u_int32_t);
> +
> +struct agp_methods agp_nvidia_methods = {
> + agp_nvidia_get_aperture,
> + agp_nvidia_set_aperture,
> + agp_nvidia_bind_page,
> + agp_nvidia_unbind_page,
> + agp_nvidia_flush_tlb,
> + agp_generic_enable,
> + agp_generic_alloc_memory,
> + agp_generic_free_memory,
> + agp_generic_bind_memory,
> + agp_generic_unbind_memory,
> +};
> +
> +int
> +agp_nvidia_attach(struct agp_softc *sc, struct pci_attach_args *pa)
> +{
> + struct agp_nvidia_softc *nsc;
> + struct agp_gatt *gatt;
> + u_int32_t apbase;
> + u_int32_t aplimit;
> + pcireg_t temp;
> + int size;
> + int i;
> + int error;
> +
> + nsc = malloc(sizeof *nsc, M_AGP, M_NOWAIT);
> + if (nsc == NULL) {
> + printf(": can't allocate chipset-specific softc\n");
> + return (ENOMEM);
> + }
> + memset(nsc, 0, sizeof *nsc);
> + sc->sc_chipc = nsc;
> + sc->sc_methods = &agp_nvidia_methods;
> +
> + if (agp_map_aperture(pa, sc, AGP_APBASE, PCI_MAPREG_TYPE_MEM) != 0) {
> + printf(": failed to map aperture\n");
> + free(nsc, M_DEVBUF);
> + sc->sc_chipc = NULL;
> + return (ENXIO);
> + }
> +
> + switch (PCI_PRODUCT(pa->pa_id)) {
> + case PCI_PRODUCT_NVIDIA_NFORCE_PCHB:
> + nsc->wbc_mask = 0x00010000;
> + break;
> + case PCI_PRODUCT_NVIDIA_NFORCE2_PCHB:
> + nsc->wbc_mask = 0x80000000;
> + break;
> + default:
> + printf(": unknown product id %#x\n", PCI_PRODUCT(pa->pa_id));
> + free(nsc, M_DEVBUF);
> + sc->sc_chipc = NULL;
> + return (ENODEV);
> + }
> +
> + /* AGP Controller */
> + nsc->tag = pa->pa_tag;
> +
> + /* Memory Controller 1 */
> + nsc->mc1_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, 0, 1);
> + /* XXX Validate existence */
> +
> + /* Memory Controller 2 */
> + nsc->mc2_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, 0, 2);
> + /* XXX Validate existence */
> +
> + /* AGP Host to PCI Bridge */
> + nsc->btag = pci_make_tag(pa->pa_pc, pa->pa_bus, 30, 0);
> + /* XXX Validate existence */
> +
> + nsc->initial_aperture = AGP_GET_APERTURE(sc);
> +
> + for (;;) {
> + gatt = agp_alloc_gatt(sc);
> + if (gatt != NULL)
> + break;
> + /*
> + * Probably contigmalloc failure. Try reducing the
> + * aperture so that the gatt size reduces.
> + */
> + if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
> + free(nsc, M_DEVBUF);
> + sc->sc_chipc = NULL;
> + return (ENOMEM);
> + }
> + }
> + nsc->gatt = gatt;
> +
> + apbase = sc->sc_apaddr;
> + aplimit = apbase + AGP_GET_APERTURE(sc) - 1;
> + pci_conf_write(sc->sc_pc, nsc->mc2_tag, AGP_NVIDIA_2_APBASE, apbase);
> + pci_conf_write(sc->sc_pc, nsc->mc2_tag, AGP_NVIDIA_2_APLIMIT, aplimit);
> + pci_conf_write(sc->sc_pc, nsc->btag, AGP_NVIDIA_3_APBASE, apbase);
> + pci_conf_write(sc->sc_pc, nsc->btag, AGP_NVIDIA_3_APLIMIT, aplimit);
> +
> + error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(sc));
> + if (error) {
> + printf("Failed to setup IORRs\n");
> + agp_free_gatt(sc, gatt);
> + free(nsc, M_DEVBUF);
> + sc->sc_chipc = NULL;
> + return (ENXIO);
> + }
> +
> + /* directory size is 64k */
> + size = AGP_GET_APERTURE(sc) / 1024 / 1024;
> + nsc->num_dirs = size / 64;
> + nsc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
> + nsc->pg_offset = 0;
> + if (nsc->num_dirs == 0) {
> + nsc->num_dirs = 1;
> + nsc->num_active_entries /= (64 / size);
> + nsc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
> + ~(AGP_GET_APERTURE(sc) - 1)) / PAGE_SIZE;
> + }
> +
> + /* (G)ATT Base Address */
> + for (i = 0; i < 8; i++) {
> + pci_conf_write(sc->sc_pc, nsc->mc2_tag, AGP_NVIDIA_2_ATTBASE(i),
> + (nsc->gatt->ag_physical +
> + (i % nsc->num_dirs) * 64 * 1024) | 1);
> + }
> +
> + /* GTLB Control */
> + temp = pci_conf_read(sc->sc_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL);
> + pci_conf_write(sc->sc_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL, temp | 0x11);
> +
> + /* GART Control */
> + temp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_NVIDIA_0_APSIZE);
> + pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_NVIDIA_0_APSIZE, temp | 0x100);
> +
> + return (0);
> +}
> +
> +#if 0
> +static int
> +agp_nvidia_detach(struct agp_softc *sc)
> +{
> + struct agp_nvidia_softc *nsc = sc->sc_chipc;
> + int error;
> + pcireg_t temp;
> +
> + error = agp_generic_detach(sc);
> + if (error)
> + return (error);
> +
> + /* GART Control */
> + temp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_NVIDIA_0_APSIZE);
> + pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_NVIDIA_0_APSIZE, temp & ~0x100);
> +
> + /* GTLB Control */
> + temp = pci_conf_read(sc->sc_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL);
> + pci_conf_write(sc->sc_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL, temp & ~0x11);
> +
> + /* Put the aperture back the way it started. */
> + AGP_SET_APERTURE(sc, nsc->initial_aperture);
> +
> + /* restore iorr for previous aperture size */
> + nvidia_init_iorr(sc->sc_apaddr, nsc->initial_aperture);
> +
> + agp_free_gatt(sc, nsc->gatt);
> +
> + return (0);
> +}
> +#endif
> +
> +static u_int32_t
> +agp_nvidia_get_aperture(struct agp_softc *sc)
> +{
> + pcireg_t reg;
> +
> + reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_NVIDIA_0_APSIZE);
> + reg &= 0xf;
> + switch (reg) {
> + case 0: return (512 * 1024 * 1024); break;
> + case 8: return (256 * 1024 * 1024); break;
> + case 12: return (128 * 1024 * 1024); break;
> + case 14: return (64 * 1024 * 1024); break;
> + case 15: return (32 * 1024 * 1024); break;
> + default:
> + printf("Invalid aperture setting 0x%x", reg);
> + return 0;
> + }
> +}
> +
> +static int
> +agp_nvidia_set_aperture(struct agp_softc *sc, u_int32_t aperture)
> +{
> + u_int8_t val;
> + u_int8_t key;
> +
> + switch (aperture) {
> + case (512 * 1024 * 1024): key = 0; break;
> + case (256 * 1024 * 1024): key = 8; break;
> + case (128 * 1024 * 1024): key = 12; break;
> + case (64 * 1024 * 1024): key = 14; break;
> + case (32 * 1024 * 1024): key = 15; break;
> + default:
> + printf("Invalid aperture size (%dMb)\n", aperture / 1024 / 1024);
> + return (EINVAL);
> + }
> + val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_NVIDIA_0_APSIZE);
> + val &= ~0xf;
> + val |= key;
> + pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_NVIDIA_0_APSIZE, val);
> +
> + return (0);
> +}
> +
> +static int
> +agp_nvidia_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
> +{
> + struct agp_nvidia_softc *nsc = sc->sc_chipc;
> + u_int32_t index;
> +
> + if (offset < 0 || offset >= (nsc->gatt->ag_entries << AGP_PAGE_SHIFT))
> + return (EINVAL);
> +
> + index = (nsc->pg_offset + offset) >> AGP_PAGE_SHIFT;
> + nsc->gatt->ag_virtual[index] = physical | 1;
> +
> + return (0);
> +}
> +
> +static int
> +agp_nvidia_unbind_page(struct agp_softc *sc, off_t offset)
> +{
> + struct agp_nvidia_softc *nsc = sc->sc_chipc;
> + u_int32_t index;
> +
> + if (offset < 0 || offset >= (nsc->gatt->ag_entries << AGP_PAGE_SHIFT))
> + return (EINVAL);
> +
> + index = (nsc->pg_offset + offset) >> AGP_PAGE_SHIFT;
> + nsc->gatt->ag_virtual[index] = 0;
> +
> + return (0);
> +}
> +
> +static void
> +agp_nvidia_flush_tlb(struct agp_softc *sc)
> +{
> + struct agp_nvidia_softc *nsc = sc->sc_chipc;
> + u_int32_t wbc_reg, temp;
> + volatile u_int32_t *ag_virtual;
> + int i;
> +
> + if (nsc->wbc_mask) {
> + wbc_reg = pci_conf_read(sc->sc_pc, nsc->mc1_tag, AGP_NVIDIA_1_WBC);
> + wbc_reg |= nsc->wbc_mask;
> + pci_conf_write(sc->sc_pc, nsc->mc1_tag, AGP_NVIDIA_1_WBC, wbc_reg);
> +
> + /* Wait no more than 3 seconds. */
> + for (i = 0; i < 3000; i++) {
> + wbc_reg = pci_conf_read(sc->sc_pc, nsc->mc1_tag, AGP_NVIDIA_1_WBC);
> + if ((nsc->wbc_mask & wbc_reg) == 0)
> + break;
> + else
> + DELAY(1000);
> + }
> + if (i == 3000)
> + printf("TLB flush took more than 3 seconds.\n");
> + }
> +
> + ag_virtual = (volatile u_int32_t *)nsc->gatt->ag_virtual;
> +
> + /* Flush TLB entries. */
> + for(i = 0; i < 32 + 1; i++)
> + temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
> + for(i = 0; i < 32 + 1; i++)
> + temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
> +}
> +
> +#define SYSCFG 0xC0010010
> +#define IORR_BASE0 0xC0010016
> +#define IORR_MASK0 0xC0010017
> +#define AMD_K7_NUM_IORR 2
> +
> +static int
> +nvidia_init_iorr(u_int32_t addr, u_int32_t size)
> +{
> + quad_t base, mask, sys;
> + u_int32_t iorr_addr, free_iorr_addr;
> +
> + /* Find the iorr that is already used for the addr */
> + /* If not found, determine the uppermost available iorr */
> + free_iorr_addr = AMD_K7_NUM_IORR;
> + for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
> + base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
> + mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
> +
> + if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
> + break;
> +
> + if ((mask & 0x00000800ULL) == 0)
> + free_iorr_addr = iorr_addr;
> + }
> +
> + if (iorr_addr >= AMD_K7_NUM_IORR) {
> + iorr_addr = free_iorr_addr;
> + if (iorr_addr >= AMD_K7_NUM_IORR)
> + return (EINVAL);
> + }
> +
> + base = (addr & ~0xfff) | 0x18;
> + mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
> + wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
> + wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
> +
> + sys = rdmsr(SYSCFG);
> + sys |= 0x00100000ULL;
> + wrmsr(SYSCFG, sys);
> +
> + return (0);
> +}
> Index: sys/dev/pci/agpreg.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/agpreg.h,v
> retrieving revision 1.10
> diff -u -r1.10 agpreg.h
> --- sys/dev/pci/agpreg.h 23 Mar 2008 08:36:41 -0000 1.10
> +++ sys/dev/pci/agpreg.h 1 Sep 2008 02:45:25 -0000
> -266,4 +266,17
> #define AGP_G33_PGTBL_SIZE_1M (1U << 8)
> #define AGP_G33_PGTBL_SIZE_2M (2U << 8)
>
> +/*
> + * NVIDIA nForce/nForce2 registers
> + */
> +#define AGP_NVIDIA_0_APBASE 0x10
> +#define AGP_NVIDIA_0_APSIZE 0x80
> +#define AGP_NVIDIA_1_WBC 0xf0
> +#define AGP_NVIDIA_2_GARTCTRL 0xd0
> +#define AGP_NVIDIA_2_APBASE 0xd8
> +#define AGP_NVIDIA_2_APLIMIT 0xdc
> +#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
> +#define AGP_NVIDIA_3_APBASE 0x50
> +#define AGP_NVIDIA_3_APLIMIT 0x54
> +
> #endif /* !_PCI_AGPREG_H_ */
> Index: sys/dev/pci/agpvar.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/agpvar.h,v
> retrieving revision 1.14
> diff -u -r1.14 agpvar.h
> --- sys/dev/pci/agpvar.h 12 Jul 2008 17:31:06 -0000 1.14
> +++ sys/dev/pci/agpvar.h 1 Sep 2008 06:05:14 -0000
> -207,6 +207,7
> int agp_amd_attach(struct agp_softc *, struct pci_attach_args *);
> int agp_i810_attach(struct agp_softc *, struct pci_attach_args *);
> int agp_intel_attach(struct agp_softc *, struct pci_attach_args *);
> +int agp_nvidia_attach(struct agp_softc *, struct pci_attach_args *);
> int agp_via_attach(struct agp_softc *, struct pci_attach_args *);
> int agp_sis_attach(struct agp_softc *, struct pci_attach_args *);
>
> Index: sys/dev/pci/files.agp
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/files.agp,v
> retrieving revision 1.2
> diff -u -r1.2 files.agp
> --- sys/dev/pci/files.agp 16 Mar 2008 19:00:28 -0000 1.2
> +++ sys/dev/pci/files.agp 1 Sep 2008 03:00:10 -0000
> -17,6 +17,9
> define agp_intel
> file dev/pci/agp_intel.c agp_intel & agpbus needs-flag
>
> +define agp_nvidia
> +file dev/pci/agp_nvidia.c agp_nvidia & agpbus needs-flag
> +
> define agp_sis
> file dev/pci/agp_sis.c agp_sis & agpbus needs-flag
>
> ------------------------------------------------------------------------------
>
> dmesg:
> ------------------------------------------------------------------------------
> OpenBSD 4.4-current (GENERIC+nvagp) #0: Mon Sep 1 19:11:49 PDT 2008
> clamatbluesong.XXXXXXXXXXXX:/sys/arch/i386/compile/GENERIC+nvagp
> cpu0: AMD Athlon(tm) XP 2800+ ("AuthenticAMD" 686-class, 512KB L2 cache) 2.08 GHz
> cpu0: FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,MMX,FXSR,SSE
> real mem = 2146988032 (2047MB)
> avail mem = 2067615744 (1971MB)
> mainbus0 at root
> bios0 at mainbus0: AT/286+ BIOS, date 08/02/04, BIOS32 rev. 0 0xfbba0, SMBIOS rev. 2.3 0xf0000 (37 entries)
> bios0: vendor Phoenix Technologies, LTD version "6.00 PG" date 08/02/2004
> bios0: MICRO-STAR INTERNATIONAL CO., LTD MS-6570
> apm0 at bios0: Power Management spec V1.2 (slowidle)
> apm0: AC on, battery charge unknown
> acpi at bios0 function 0x0 not configured
> pcibios0 at bios0: rev 2.1 0xf0000/0xdb04
> pcibios0: PCI IRQ Routing Table rev 1.0 0xfda40/192 (10 entries)
> pcibios0: PCI Exclusive IRQs: 7 10 11 14 15
> pcibios0: no compatible PCI ICU found
> pcibios0: Warning, unable to fix up PCI interrupt routing
> pcibios0: PCI bus #2 is the last bus
> bios0: ROM list: 0xc0000/0xd000 0xd0000/0x4000
> cpu0 at mainbus0
> pci0 at mainbus0 bus 0: configuration mode 1 (no bios)
> pchb0 at pci0 dev 0 function 0 "NVIDIA nForce2 PCI" rev 0xc1
> "NVIDIA nForce2" rev 0xc1 at pci0 dev 0 function 1 not configured
> "NVIDIA nForce2" rev 0xc1 at pci0 dev 0 function 2 not configured
> "NVIDIA nForce2" rev 0xc1 at pci0 dev 0 function 3 not configured
> "NVIDIA nForce2" rev 0xc1 at pci0 dev 0 function 4 not configured
> "NVIDIA nForce2" rev 0xc1 at pci0 dev 0 function 5 not configured
> pcib0 at pci0 dev 1 function 0 "NVIDIA nForce2 ISA" rev 0xa3
> nviic0 at pci0 dev 1 function 1 "NVIDIA nForce2 SMBus" rev 0xa2
> iic0 at nviic0
> iic0: addr 0x1b 06=f0 08=03 09=03 0b=7f 0c=08 0d=08 0e=f0 0f=07 10=0c 11=03 14=55 15=55 17=ff 18=ff 1c=02 20=7f 22=07 26=30 29=ff words 00=00ff 01=00ff 02=00ff 03=00ff 04=00ff 05=00ff 06=f0ff 07=00ff
> iic0: addr 0x2f 04=00 06=02 07=00 0c=00 0d=07 0e=84 0f=00 10=ca 11=10 12=00 13=60 14=14 15=62 16=01 17=06 words 00=ffff 01=ffff 02=ffff 03=ffff 04=00ff 05=ffff 06=02ff 07=00ff
> spdmem0 at iic0 addr 0x50: 1GB DDR SDRAM non-parity PC3200CL3.0
> spdmem1 at iic0 addr 0x51: 1GB DDR SDRAM non-parity PC3200CL3.0
> iic1 at nviic0
> ohci0 at pci0 dev 2 function 0 "NVIDIA nForce2 USB" rev 0xa3: irq 15, version 1.0, legacy support
> ohci1 at pci0 dev 2 function 1 "NVIDIA nForce2 USB" rev 0xa3: irq 7, version 1.0, legacy support
> ehci0 at pci0 dev 2 function 2 "NVIDIA nForce2 USB" rev 0xa3: irq 14
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 "NVIDIA EHCI root hub" rev 2.00/1.00 addr 1
> ppb0 at pci0 dev 8 function 0 "NVIDIA nForce2 PCI-PCI" rev 0xa3
> pci1 at ppb0 bus 1
> siop0 at pci1 dev 7 function 0 "Symbios Logic 53c1010-33" rev 0x01: irq 15, using 8K of on-board RAM
> scsibus0 at siop0: 16 targets, initiator 7
> sd0 at scsibus0 targ 5 lun 0: <IBM-ESXS, DTN036W3UWDY10FN, S23J> SCSI3 0/direct fixed
> sd0: 34715MB, 512 bytes/sec, 71096640 sec total
> sd1 at scsibus0 targ 6 lun 0: <IBM-ESXS, DTN036W3UWDY10FN, S23J> SCSI3 0/direct fixed
> sd1: 34715MB, 512 bytes/sec, 71096640 sec total
> sd2 at scsibus0 targ 15 lun 0: <IBM, DDYS-T18350N, S96H> SCSI3 0/direct fixed
> sd2: 17501MB, 512 bytes/sec, 35843670 sec total
> siop1 at pci1 dev 7 function 1 "Symbios Logic 53c1010-33" rev 0x01: irq 11, using 8K of on-board RAM
> scsibus1 at siop1: 16 targets, initiator 7
> cd0 at scsibus1 targ 2 lun 0: <PLEXTOR, CD-R PX-W124TS, 1.07> SCSI2 5/cdrom removable
> st0 at scsibus1 targ 4 lun 0: <ECRIX, VXA-1, 2959> SCSI2 1/sequential removable
> vr0 at pci1 dev 8 function 0 "VIA VT6105 RhineIII" rev 0x86: irq 11, address 00:05:5d:80:c4:8d
> ukphy0 at vr0 phy 1: Generic IEEE 802.3u media interface, rev. 4: OUI 0x004063, model 0x0034
> eap0 at pci1 dev 9 function 0 "Ensoniq AudioPCI" rev 0x00: irq 10
> audio0 at eap0
> midi0 at eap0: <AudioPCI MIDI UART>
> pciide0 at pci0 dev 9 function 0 "NVIDIA nForce2 IDE" rev 0xa2: DMA, channel 0 configured to compatibility, channel 1 configured to compatibility
> pciide0: channel 0 ignored (disabled)
> pciide0: channel 1 ignored (disabled)
> ppb1 at pci0 dev 30 function 0 "NVIDIA nForce2 AGP" rev 0xc1
> pci2 at ppb1 bus 2
> vga1 at pci2 dev 0 function 0 "ATI Radeon 9600 Pro" rev 0x00
> wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
> wsdisplay0: screen 1-5 added (80x25, vt100 emulation)
> agp0 at vga1: aperture at 0xe0000000, size 0x4000000
> radeondrm0 at vga1 ATI Radeon AP 9600(0), 1.29.0 20080613
> "ATI Radeon 9600 Pro Sec" rev 0x00 at pci2 dev 0 function 1 not configured
> isa0 at pcib0
> isadma0 at isa0
> com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
> com1 at isa0 port 0x2f8/8 irq 3: ns16550a, 16 byte fifo
> pckbc0 at isa0 port 0x60/5
> pckbd0 at pckbc0 (kbd slot)
> pckbc0: using irq 1 for kbd slot
> wskbd0 at pckbd0: console keyboard, using wsdisplay0
> pmsi0 at pckbc0 (aux slot)
> pckbc0: using irq 12 for aux slot
> wsmouse0 at pmsi0 mux 0
> pcppi0 at isa0 port 0x61
> midi1 at pcppi0: <PC speaker>
> spkr0 at pcppi0
> wbsio0 at isa0 port 0x4e/2: W83627HF rev 0x17
> lm1 at wbsio0 port 0x290/8: W83627HF
> npx0 at isa0 port 0xf0/16: reported by CPUID; using exception 16
> fdc0 at isa0 port 0x3f0/6 irq 6 drq 2
> fd0 at fdc0 drive 0: 1.44MB 80 cyl, 2 head, 18 sec
> usb1 at ohci0: USB revision 1.0
> uhub1 at usb1 "NVIDIA OHCI root hub" rev 1.00/1.00 addr 1
> usb2 at ohci1: USB revision 1.0
> uhub2 at usb2 "NVIDIA OHCI root hub" rev 1.00/1.00 addr 1
> biomask ebe5 netmask ebe5 ttymask fbff
> mtrr: Pentium Pro MTRR support
> uhub3 at uhub0 port 4 "Standard Microsystems product 0x2514" rev 2.00/0.00 addr 2
> udsbr0 at uhub2 port 1 "GemTek Corp USB FM Radio" rev 1.00/4.10 addr 2
> radio0 at udsbr0
> softraid0 at root
> siop0: target 5 now using tagged DT 16 bit 80.0 MHz 62 REQ/ACK offset xfers
> siop0: target 6 now using tagged DT 16 bit 80.0 MHz 62 REQ/ACK offset xfers
> siop0: target 15 now using tagged DT 16 bit 80.0 MHz 62 REQ/ACK offset xfers
> root on sd0a swap on sd0b dump on sd0b
> info: [drm] Setting GART location based on new memory map
> info: [drm] Loading R300 Microcode
> info: [drm] Num pipes: 1
> info: [drm] writeback test succeeded in 1 usecs
> info: [drm] Num pipes: 1
> info: [drm] Setting GART location based on new memory map
> info: [drm] Loading R300 Microcode
> info: [drm] Num pipes: 1
> info: [drm] writeback test succeeded in 1 usecs
> info: [drm] Num pipes: 1
> info: [drm] Setting GART location based on new memory map
> info: [drm] Loading R300 Microcode
> info: [drm] Num pipes: 1
> info: [drm] writeback test succeeded in 1 usecs
> siop1: target 4 now using 8 bit 10.0 MHz 31 REQ/ACK offset xfers
> umass0 at uhub0 port 1 configuration 1 interface 0 "Genesys Logic USB2.0 card Reader" rev 2.00/91.44 addr 3
> umass0: using SCSI over Bulk-Only
> scsibus2 at umass0: 2 targets, initiator 0
> sd3 at scsibus2 targ 1 lun 0: <Generic, STORAGE DEVICE, 9144> SCSI0 0/direct removable
> sd3: drive offline
> sd4 at scsibus2 targ 1 lun 1: <Generic, STORAGE DEVICE, 9144> SCSI0 0/direct removable
> sd4: drive offline
> sd5 at scsibus2 targ 1 lun 2: <Generic, STORAGE DEVICE, 9144> SCSI0 0/direct removable
> sd5: drive offline
> sd6 at scsibus2 targ 1 lun 3: <Generic, STORAGE DEVICE, 9144> SCSI0 0/direct removable
> sd6: drive offline
> sd7 at scsibus2 targ 1 lun 4: <Generic, STORAGE DEVICE, 9144> SCSI0 0/direct removable
> sd7: drive offline
> umass1 at uhub3 port 2 configuration 1 interface 0 "LEXAR MEDIA JUMPDRIVE PRO" rev 2.00/0.00 addr 4
> umass1: using SCSI over Bulk-Only
> scsibus3 at umass1: 2 targets, initiator 0
> sd8 at scsibus3 targ 1 lun 0: <LEXAR, JUMPDRIVE PRO, 0> SCSI2 0/direct removable
> sd8: 246MB, 512 bytes/sec, 503808 sec total
> sd8 detached
> scsibus3 detached
> umass1 detached
> ------------------------------------------------------------------------------
>
> --
> Debugging is twice as hard as writing the code in the first place.
> Therefore, if you write the code as cleverly as possible, you are, by
> definition, not smart enough to debug it. -- Kernighan
> -- quoted by Quentyn Taylor

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